1. Field of the Invention
The present invention relates to a semiconductor device having a pn junction, and more particularly, a semiconductor device and a resistor having a structure where an insulative isolator is provided on a semiconductor film disposed on an insulative substrate on the opposite side to the substrate without making contact with the substrate.
2. Description of the Background Art
Proposals for a so-called SOI (Silicon On Insulator) structure have been made conventionally. FIG. 62 is a sectional view exemplifying a structure of a CMOS (Complementary Metal Oxide Semiconductor) transistor 200 having the SOI structure. A P− type semiconductor layer 20 is provided on an insulator 9, and an insulative isolator 40 is provided separately from the insulator 9 on a surface of the semiconductor layer 20 on the far side from the insulator 9. Such an isolator that is separated from the insulator and provided on the surface of the semiconductor film disposed on the insulator for isolating the surface of the semiconductor layer is hereinafter tentatively referred to as “partial isolator”.
N+ type source/drain layers 21 and 22 are provided in the semiconductor layer 20. These source/drain layers and a gate electrode 23 provided on the semiconductor layer 20 with a gate insulating film interposed therebetween constitute an NMOS transistor 2. Such an NMOS transistor having the SOI structure including the partial isolator is disclosed in “Bulk-Layout-Compatible 0.18 μm SOI-CMOS Technology Using Body-Fixed Partial Trench Isolation (PTI)” (Y. Hirano et al., 1999 IEEE International SOI Conference, October 1999, pp. 131-132), for example.
An N− type semiconductor layer 10 is further provided on the insulator 9. P+ type source/drain layers 11 and 12 provided in the semiconductor layer 10 and a gate electrode 13 provided on the semiconductor layer 10 with a gate insulating film interposed therebetween constitute a PMOS transistor 1.
The source/drain layer 22 extends through the semiconductor layer 20, and the source/drain layer 12 extends through the semiconductor layer 10 in the thickness direction, respectively, to divide the respective semiconductor layers 10 and 20 in a sectional view. There is a semiconductor layer 20t being a part of the semiconductor layer 20 and a semiconductor layer 10t being a part of the semiconductor layer 10 between the source/drain layers 12 and 22. The semiconductor layers 20t and 10t are adjacent to each other to form a pn junction J1 under the partial isolator 40, that is, between the partial isolator and the insulator 9. The pn junction J1 is positioned in the above-described manner when, for example, the pn junction J1 is formed at the stage of forming the semiconductor layers 10 and 20 before forming the partial isolator 40 and the partial isolator 40 is then formed on a boundary between the semiconductor layers 10 and 20.
In this way, semiconductor layers of conductivity types different from each other, i.e., p and n type semiconductor layers are formed as a semiconductor film having the SOI structure in a general LSI (Large Scale Integrated Circuit), and a MOS transistor and a bipolar transistor are formed using these semiconductor layers.
However, it is observed in the structure shown in FIG. 62 that the pn junction J1 positioned under the partial isolator 40 results in occurrence of an abnormal leakage current at the pn junction J1.